Flash memory devices store information with high density on Flash cells with ever smaller dimensions. In addition, Multi-Level Cells (MLC) store several bits per cell by setting the amount of charge in a cell. Flash memory devices are organized into (physical) pages. Each page includes a section allocated for data (512 bytes-16 Kbytes and expected larger in the future) and a small amount of spare bytes (64-1 Kbytes or more bytes for every page) for storing redundancy and metadata. The redundancy bytes are used to store error correcting information, for correcting errors which may have occurred during flash lifetime and the page read process. Each program operation is performed on an entire page. A number of pages are grouped together to form an Erase Block (erase block). A page cannot be erased unless the entire erase block which contains it is erased.
One common application of flash memory devices is Secure Digital (SD) cards and embedded Multi-Media Cards (eMMC). An embedded flash memory storage device (like eMMC card) may typically contain flash memory devices and a flash memory controller. The memory controller translates commands coming in through the host interface into actions (Read/Write/Erase) on the flash memory devices. The most common commands for memory storage device may be Read and Write commands of one or more sectors, where a sector may be, but is not limited to, a sequence of 512 bytes. The Read or Write commands may be of a single sector or multiple sectors. These commands may refer to logical addresses. These addresses may then be redirected to new addresses on the flash memory which need not directly correspond to the logical addresses that might be referenced by the Read or Write commands. This is due to memory management that may be carried out by the flash memory controller in order to support several features such as wear-leveling, bad block management, firmware code and data, error-correction, and others. The erase function is performed on an entire erase block. Because of this functionality, before the data of a certain block may be replaced such as during a write function, the new data must be written in an alternative location before an erase can occur, to preserve the integrity of the stored data.
Due to the small dimensions of a typical SD or eMMC card and the price limitations, the memory controller may typically have only a small RAM available for storage. The small size of the RAM memory limits the type of memory management which may be carried out by the memory controller with regard to the data stored in the flash memory device and received from the interface.
The memory controller may typically manage the memory at the erase block level, because managing data of small particle sizes becomes difficult. That is, the logical memory space may be divided into units of memory contained within a single erase block or some constant multiple of erase blocks, such that all logical sector addresses within each said unit of memory may be mapped to the same erase block or some constant multiple thereof.
This type of management has the drawback that for writing random access data sectors to memory or other memory units smaller than an erase block, erase blocks must be frequently rewritten. Because of the characteristics of flash memory, each new piece of information is written into an empty page. In flash memory a page may not be rewritten before the entire erase block is erased first.
If a portion of the memory unit contained within an erase block may need to be rewritten, it is first written into a freshly allocated erased erase block. The remaining, unmodified, contents of the erase block may then be copied into the new erase block and the former erase-block may be declared as free and may be further erased. This operation may be referred to as “sealing” or “merging”. The operation involves collecting the most recent data of a logical block and then merging it with the rest of the block data in a single erase block. Thus, even if a single sector from an erase block is rewritten, a complete erase block would be rewritten.
This may result in causing a significant degradation in the average write speed. It may also impose a significant delay in the response time between random write sector operations. It also may cause excessive P/E (program/erase) cycling, which may be problematic in new generations of flash memory devices where the number of P/E cycles is limited to a few thousand or even a few hundreds.
The memory controller is used to manage the overhead described above, and must always keep track of the data associated with each logical address and the actual memory location. This is usually achieved by implementing a mapping method between the logical address space assigned to the data and the actual memory storage location of the data.
Several methods may be implemented to execute such a mapping. Two approaches implement mapping systems that rely on block mapping and page mapping, respectively. In an approach using block mapping (block based management), each physical block in the flash memory is mapped to a contiguous logical memory block of the same data size (LMBA). In this approach when one page in some logical block is updated, the entire associated physical block must be copied to a fresh block, and the new data must be written in place of the obsolete copy. A merge may be an operation where the original content of a logical block is merged with the new data to form a new up to date copy of the block. This up to date copy is the data block that is associated with a logical data block assigned to the data contained within. In the second approach, each logical page (usually but not necessary 4 KB of data) of a logical block is mapped to an arbitrary physical page where two pages belonging to the same logical block can reside in different physical blocks of the flash memory. The second approach (page based management) requires additional complexity in terms of the amount of management data and memory overhead required for the physical memory to logical address mapping tables. For memory applications where severe limitations exist on available control memory, this approach is less appropriate. Flash memories such as SD or eMMC have limited amount of memory overhead and the first mapping approach, or variants thereof are more practical.
In order to be able to benefit from the advantages of both aforementioned flash management approaches, embedded device can manage main part of the device capacity in a block based manner, while managing a smaller portion in a page based manner. Such approach allows to keep most of the device capacity (according to the size allocated for the device user/host) mapped with rather compact tables, translating logical address of a large contiguous span of memory to a physical location (logical to physical blocks mapping), therefore using less RAM memory, and minimizing the need to access flash for storing and loading such tables or their derivatives. In parallel such approach (page based random data cache portion) allows overcoming problems relevant to writing of random traffic as described above (performance degradation, delay in response time, excessive P/E cycling etc.). Typically some sort of cleaning algorithms should be applied constantly or from time to time in order to vacate data from the random data cache or move data in the cache and free space available for further absorbing random data. Efficiency of cleaning algorithms, capacity available for caching random data (overprovisioning) and the efficiency of the random write operations determines the random write performance of the device.
Overprovisioning—usually there's a difference between the physical flash capacity used by the device and the logical capacity available for the device user. This difference allows the memory controller to use some of the device capacity for internal management needs. Overprovisioning in embedded flash memory storage systems is typically defined statically and doesn't change over system's lifetime.
Overprovisioning influences Random Write performance—one of the purposes of the capacity not allocated for the user (overprovisioning) is to allow caching of random write traffic (short, non-sequential write transactions). Increase in overprovisioning capacity typically will result in Random Write performance improvement due to ability to perform cleaning of the cached (page based) data to block based mapped data less frequently.
Another host interface command that can be exploited by the flash memory storage system is a logical erase operation, usually called “Trim”. In this command the host provides the flash memory controller logical address space which was typically previously written by the host and the user data in it is no longer required. This logical address range is declared as logically erased and storing no valid user data.
The invention suggests that partially written user space (unused since the device life start or trimmed by the device user or available due to changing redundancy rate, to handle different reliability requirements over device lifetime) can free additional temporary overprovisioning.
Some of the data in a typical flash memory device may be stored in a single cell manner (SLC) in order to increase the performance or the reliability of the stored information. E.g. metadata (system control information/mapping tables etc.), enhanced storage partition, random data caches etc.
Typical flash memory device memory controller needs to account for the free blocks available in the system (spare blocks). Such blocks may be signed by some software indication or managed in some software database. Collection of all or part (distinguished according to some trait) of spare blocks in the system can be regarded as “spare blocks pool” (list of such blocks). MLC/TLC devices may need to distinguish MLC spare blocks from SLC spare blocks and manage several pools of spare blocks of different types. E.g. SLC blocks may need to reach a much higher cycling than the MLC blocks.